Home » New front opening up in US-China chip battle

New front opening up in US-China chip battle

TAIPEI – US President Joe Biden has adopted a two-pronged approach to constrain China’s high-tech progress, curbing Beijing’s access to leading-edge chips while bolstering semiconductor production in the United States.

He is about to ratchet up the pressure further, shifting focus to an emerging arena of the contest for technological supremacy: the process of packaging semiconductors that is increasingly seen as a path to achieving higher performance.

Only the US is not alone is recognising the potential of so-called advanced packaging: China too is capitalising on an area that is not subject to sanctions, capturing global market share, and achieving progress denied it in manufacturing high-end chips.

Up until very recently, the business of packaging semiconductors – encasing chips in materials that both protect them and connect them to the electronic device they are part of – was, at best, an afterthought for the industry. So it was outsourced, mainly to Asia, with China a prime beneficiary. Today, the US accounts for just 3 per cent of the world’s packaging capacity, according to Intel.

Yet suddenly, advanced packaging is everywhere: Intel is banking on it as a core part of the US chip giant’s strategy to return to competitiveness; China sees it as a means of building out domestic semiconductor capacity; and now Washington is turning to it as part of its own plans for self-sufficiency.

More than a year after the CHIPS and Science Act came into being, the Biden administration has outlined plans for a US$3 billion (S$4 billion) National Advanced Packaging Manufacturing Programme, after recently tapping a director for the centre. The goal is to create multiple high-volume packaging facilities by the end of the decade, said Under Secretary of State of Commerce Laurie Locascio – and reduce reliance on Asian supply lines that pose a security risk the US “just can’t accept”.

With advanced packaging rapidly becoming a new front in the global conflict over chips, some argue it is long overdue.

Assembly, testing and packaging – usually considered together as “back-end” manufacturing – was always the least glamorous end of the semiconductor industry, with less innovation and lower added value than the “front end” business of making chips with features measured in the billionths of a metre. Yet the level of sophistication is rising fast as new technologies enable chips to be combined, stacked and their performance enhanced in what industry executives are calling an inflection point.

Advanced packaging cannot help China compete with leading-edge semiconductor developments from the US, but it allows Beijing to build faster, cheaper systems for computing by stitching together different chips closely together. In that case China could save its latest chip technology, which is expensive and likely available in limited volume, for the most important part of the chip and use older, cheaper technologies to make chips that carry out other functions like battery management and sensor controls, combining the whole in a powerful package.

Beijing has long made a strategic priority of semiconductor packaging technologies, including in President Xi Jinping’s Made in China programme announced in 2015. China has 38 per cent of the world’s assembly, testing and packaging market, the most of any nation, according to the US-based Semiconductor Industry Association.

China already boasts the most back-end facilities by number, including the world’s third-largest assembly and testing company, JCET Group, which trails only Taiwan’s ASE Group and Amkor Technology of the US in revenue. What’s more, Chinese companies are building market share, including through JCET’s acquisition of an advanced facility in Singapore and construction of an advanced packaging plant in its hometown of Jiangyin.

One reason for the sudden focus on that special sauce is its necessity to the kind of high-power semiconductors needed for artificial intelligence applications. Indeed, a shortage of a particular type of packaging known as Chip on Wafer on Substrate, or CoWoS, is a key bottleneck in the production of Nvidia’s AI chips.

The number of chips shipped that use advanced packaging is forecast to increase ten-fold in the next 18 months – but that could soar to 100 times if it becomes standard in smartphones, Jeffries analysts Mark Lipacis and Vedvati Shrotre wrote in a Sept 14 report that classed the technology as part of a “tectonic shift” in the industry.